1. Field of the Invention
The present invention relates to a solid state image pickup device represented by a CMOS image sensor and a camera system.
2. Description of Related Art
A CMOS image sensor has been paid attention as a solid state image pickup device (image sensor) to be substituted for CCD.
This is because the CMOS image sensor overcomes various issues of CCD, including the necessity for dedicated processes for manufacturing CCD pixels and for a plurality of power source voltages for the operation, and a very complicated system because a plurality of peripheral IC's are required to be combined for the operation.
A CMOS image sensor has a plurality of large merits: manufacturing processes similar to those for a general CMOS type integrated circuit can be used for manufacturing CMOS image sensors, a single power source can drive a CMOS image sensor, and the number of peripheral IC's can be reduced because analog circuits and logic circuits manufactured by CMOS processes can be used by being mixed on the same chip.
A main trend of a CCD output circuit is a one channel (1-ch) output using a floating diffusion (FD) amplifier having an FD layer.
In contrast, a main trend of a CMOS image sensor is a column parallel output type in which each pixel is provided with an FD amplifier, and by selecting each row of a pixel array, outputs of FD amplifiers are read in a column direction at the same time.
It is difficult for only an FD amplifier disposed in each pixel to obtain a sufficient drive ability so that a data rate is required to be lowered. In this context, it is considered that parallel processing is advantageous.
Really a variety of types have been proposed for a signal output circuit of a column parallel output type CMOS image sensor.
As a method used for pixel signal reading of a CMOS image sensor, there is a method by which signal charges to be used as an optical signal generated by a photoelectric conversion element such as a photodiode are sampled temporarily via a MOS switch disposed near the photoelectric conversion element in a capacitor, and the signal charges are read.
Noises having inverse correlation to a sampling capacitor value are generally superposed upon a sampling circuit. In a pixel, when signal charges are transferred to the sampling capacitor, the signal charges are transferred perfectly by utilizing a potential gradient so that noises will not be generated at the sampling stage. However, noises are generated at a preceding stage where a voltage level of capacity is reset to a reference value.
A typical method of eliminating these noises is correlated double sampling (CDS). With this approach, a state (reset level) immediately before signal charges are sampled is read and stored, then a signal level after sampling is read, and noises are eliminated through subtraction.
There are a variety of specific CDS methods.
Description will be made on a general CMOS image sensor.
FIG. 1 is a diagram showing an example of a pixel of a CMOS image sensor constituted of four transistors.
This pixel 10 has a photoelectric conversion element such as photodiode 11, and four transistors as active elements for one photodiode 11. The four transistors include a transfer transistor 12, an amplifier transistor 13, a select transistor 14 and a reset transistor 15.
The photodiode 11 photoelectrically converts incidence light into charges (in this example, electrons) corresponding in amount to the quantity of the incidence light.
The transfer transistor 12 is connected between the photodiode 11 and a floating diffusion FD. Upon application of a drive signal to the gate (transfer gate) via a transfer control line LTx, electrons photoelectrically converted by the photodiode 11 is transferred to the floating diffusion FD.
A gate of the amplifier transistor 13 is connected to the floating diffusion FD. The amplifier transistor 13 is connected via the select transistor 14 to a signal line LSGN, and constitutes a source follower together with a constant current source 16 outside the pixel.
An address signal is applied to the gate of the select transistor 14 via a select control line LSEL, and when the select transistor 14 turns on, the amplifier transistor 13 amplifies a potential at the floating diffusion FD to output a voltage corresponding to the potential to the output (vertical) signal line LSGN. A signal voltage output from each pixel via the signal line LSGN is output to a pixel signal read circuit.
The reset transistor 15 is connected between a power supply line LVDD and the floating diffusion FD. When a reset signal is applied to the gate via a reset control line LRST, the reset transistor resets a potential at the floating diffusion FD to a potential at the power supply line LVDD.
More specifically, when the pixel is to be reset, the transfer transistor 12 is turned on to drain charges accumulated in the photoelectric conversion element 11, and then the transfer transistor 12 is turned off to make the photoelectric conversion element 11 convert an optical signal into charges and accumulate the charges.
When data is to be read, the reset transistor 15 is turned on to reset the floating diffusion FD, and then the reset transistor 15 is turned off to output a voltage at the floating diffusion FD via the amplifier transistor 13 and select transistor 14. This output is called a P phase output.
Next, the transfer transistor 12 is turned on to transfer charges accumulated in the photoelectric conversion element 11 to the floating diffusion FD, and a voltage at the floating diffusion FD is output via the amplifier transistor 13. This output is called a D phase output.
By using a difference between the D phase output and P phase output as an image signal, it becomes possible to remove not only a variation in output DC components among pixels but also reset noises of the floating diffusion FD from the image signal.
These operations are performed for pixels of one row at the same time because the gates of, e.g., the transfer transistor 12, select transistor 14 and reset transistor 15 are connected on the row unit basis.
Really a variety of pixel signal read (output) circuits of a column parallel output type CMOS image sensor have been proposed. One of the most advanced types of this circuit has an analog-digital converter unit (hereinafter abbreviated to ADC (analog digital converter)) disposed at each column to output a digital signal as the image signal.
A CMOS image sensor mounting the column parallel ADC of this type is disclosed, for example, in W. Yang et. al., “An integrated 800×600 CMOS Image System” ISSCC Digest of Technical Papers, pp. 304-305, February, 1999 and Japanese Patent Unexamined Publication No. 2005-278135.
FIG. 2 is a block diagram showing an example of the structure of a column parallel ADC mounting solid state image pickup device (CMOS image sensor).
As shown in FIG. 2, the solid state image pickup device 20 has a pixel unit 21 as an imaging unit, a vertical scan circuit 22, a horizontal transfer scan circuit 23, a timing control circuit 24, an ADC group 25, a digital-analog conversion unit (hereinafter abbreviated to DAC (digital-analog converter)) 26, an amplifier circuit (S/A) 27 and a signal processing circuit 28.
The pixel unit 21 includes photodiodes and intra-pixel amplifiers, and is constituted of pixels such as shown in FIG. 1 disposed in a matrix shape.
In the solid state image pickup device 20, the timing control circuit 24 for generating internal clocks, the vertical scan circuit 22 for controlling row addresses and row scan and the horizontal transfer scan circuit 23 for controlling column addresses and column scan are disposed as the control circuit for sequentially reading a signal from the pixel unit 21.
The ADC group 25 has ADCs disposed at a plurality of columns, each ADC being constituted of a comparator 25-1 for comparing a reference voltage Vslop having a ramp waveform obtained by stepwise changing a reference voltage generated by DAC 26 with an analog signal obtained from a pixel at each row via a vertical signal line, a counter 25-2 for counting a comparison time, and a latch 25-3 for holding a count result.
The ADC group 25 has an n-bit digital signal conversion function, each ADC being disposed at each vertical signal line (column line) to constitute a column parallel ADC block.
An output of each latch 25-3 is connected to a horizontal transfer line 29 having, for example, a 2n-bit width.
2n amplifier circuits 27 corresponding to the horizontal transfer line 29 and a signal processing circuit 28 are disposed.
In the ADC group 25, an analog signal (potential Vsl) read to the vertical signal line is compared with the reference voltage Vslop (a slope waveform having a certain gradient and changing linearly) at the comparator 25-1 disposed at each column.
In this case, the counter 25-2 disposed at each column similar to the comparator 25-1 is in operation and changes its count in one-to-one correspondence with the potential Vslop of the ramp waveform, to thereby convert a potential (analog signal) Vsl at a vertical signal line into a digital signal.
A change in the reference voltage Vslop is used for converting a voltage change into a time change, and the converted time is counted at a certain period (clock) to convert the time into a digital value.
When the analog electric signal Vsl crosses the reference voltage Vslop, an output of the comparator 25-1 is inverted to stop an input clock to the counter 25-2 and complete AD conversion.
After completion of the above-described AD conversion period, the horizontal transfer scan circuit 23 operates to input data held in the latches 25-3 to the signal processing circuit 28 via the horizontal transfer line 29 and amplifier circuit 27 to generate a two-dimensional image.
In this manner, the column parallel output process is performed.